1. Field of the Invention
The present invention relates to the formation of device grade quantum well structures. More particularly this invention relates to dopant segregation barrier layers in quantum well structures.
2. Discussion of Related Art
Recently there has been much interest generated in the study of III-V materials for future high-speed and lower power computation applications. III-V materials in general have 50-100 times higher electron mobility than Si, and III-V quantum well field effect transistors (QWFETs) pose attractive merits over scaled Si MOSFETs. Researchers have already begun investigating the performance advantages of QWFETs fabricated from extreme high mobility materials such as, but not limited to indium antimonide (InSb), gallium arsenide (GaAs), indium gallium arsenide (InxGa1-xAs: x>0.53) and indium arsenide (InAs). InSb in particular shows great promise as an ultra-fast, very low power digital logic technology as it has the highest electron mobility and saturation velocity of any known semiconductor.
Conventional quantum well devices are characterized by employing a narrower band gap quantum well layer sandwiched between two wider band gap barrier layers. The wider band gap barrier layers serve to confine carriers in the quantum well layer, and to reduce junction leakage and transistor off-state leakage current IOFF reduction. Electrons and holes are free to move in the direction perpendicular to the crystal growth direction, but not in the direction of crystal growth, hence, are 2-dimensionally “confined” and display characteristics distinctly different than in the “open” 3-dimensional crystal.
While III-V materials generally have higher carrier mobility than Si, one disadvantage is that III-V materials generally have a lower charge carrier density than Si. Accordingly, conventional quantum well devices often include modulation doping or delta doping in a region near the quantum well channel layer such that the modulation or delta doping contributes carriers to the quantum well channel layer. However, segregation and desorption of dopants during formation of the barrier layers leads to broadening of the doping profile, thereby deteriorating the characteristics of the device. Thus, what is needed is a structure and a method for reducing segregation and desorption of dopants.
Another disadvantage with the growth of III-V materials on silicon are the crystal defects generated by lattice mismatch, polar-on-nonpolar mismatch and thermal mismatch between a III-V epitaxial layer and the substrate. When the lattice mismatch between the epitaxial layer and substrate exceeds a few percent, the strain induced by the mismatch becomes too large and defects are generated in the epitaxial layer when the epitaxial film relaxes the strain. Once the film thickness is greater than the critical thickness (film is strained below this thickness and relaxed above this thickness), the strain is relaxed by creating misfit dislocations at the film and substrate interface as well as in the epitaxial film. The epitaxial crystal defects are typically in the form of threading dislocations, stacking faults and twins (periodicity breaks where one portion of the lattice is a mirror image of another). Many defects, particularly threading dislocations and twins, tend to propagate into the quantum well structure where the semiconductor device is fabricated.
Generally, the severity of defect generation correlates to the amount of lattice mismatch between the III-V semiconductor and the substrate. For these reasons, the large lattice mismatch (approximately 19.2% between the exemplary indium antimonide (InSb) and silicon (Si) combination) typically results in an epitaxial InSb device layer having a high defect density, on the order of 1×109 cm−2 to 1×1010 cm−2. The high defect density reduces the carrier mobility theoretically possible in bulk InSb, eliminating many of the technical advantages of “InSb-on-silicon” integration for high-speed and low-power logic applications. For example the electron mobility in bulk InSb films is estimated to be approximately 76,000 cm2/Vs. However, to date, the best reported electron mobility of an InSb film formed over a silicon substrate is significantly lower, approximately 40,000-50,000 cm2/Vs.
Various buffer layers have been used in attempts to relieve the strain induced by the lattice mismatch between a substrate and the III-V device layer and thereby reduce the detrimental defect density of the device layer. For example as shown in apparatus 100 of FIG. 1A, a material forms a buffer layer 170 between a silicon substrate 110 and a III-V device layer 180. A semiconductor device 190 is then fabricated in or upon device layer 180. Various materials have been utilized as the buffer layer 170. For example, both aluminum antimonide (AlSb) and strontium titanate (SrTiO3) have been suggested as a buffer layer 170 between a silicon substrate 110 and a III-V device layer 180. In practice however, as depicted in FIG. 1B, these buffer layers are unable to prevent twins 171, threading dislocations 173 and stacking faults 175 from propagating into the III-V device layer 180 as Sins 181, threading dislocations 183, and stacking faults 185. Thus, there also remains a need for a buffer layer architecture that enables lower defect density III-V semiconductor device layers formed upon silicon substrates.